External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents clks_sharing_master_out for DDR3

Core clocks sharing master interface

Table 35.  Interface: clks_sharing_master_outInterface type: Conduit
Port Name Direction Description
clks_sharing_master_out Output This port should fanout to all the core clocks sharing slaves.

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