External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents Debugging VREFOUT Calibration Failure

  1. Ensure the address and command pins are connected correctly and that every calibrated pin has sufficient margin.
  2. Ensure that the VREFCA pins on the DDR memory component are powered up to 0.6V.

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