3.8.3. Intel® Stratix® 10 Ping Pong PHY Limitations
Ping Pong PHY uses all lanes of the address and command I/O bank as address and command. For information on pin allocations, refer to the pin-out file for your device, at Pin-Out Files for Intel FPGA Devices on www.altera.com.
An additional limitation is that I/O lanes may be left unused when you instantiate multiple pairs of Ping Pong PHY interfaces. The following diagram shows two pairs of x8 Pin Pong controllers (a total of 4 interfaces). Lanes highlighted in yellow are not driven by any memory interfaces (unused lanes and pins can still serve as general purpose I/Os). Even with some I/O lanes left unused, the Ping Pong PHY approach is still beneficial in terms of resource usage, compared to independent interfaces. Memory widths of 24 bits and 40 bits have a similar situation, while 16 bit, 32 bit, and 64 bit memory widths do not suffer this limitation.
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