13.3. Timing Issue Characteristics
Timing issues typically fall into two distinct categories:
- FPGA core timing reported issues
- External memory interface timing issues in a specific mode of operation or on a specific PCB
Timing Analyzer reports timing issues in two categories: core to core and core to IOE transfers. These timing issues include the PHY and PHY reset sections in the Timing Analyzer Report DDR subsection of timing analysis. External memory interface timing issues are specifically reported in the Timing Analyzer Report DDR subsection, excluding the PHY and PHY reset. The Report DDR PHY and PHY reset sections only include the PHY, and specifically exclude the controller, core, PHY-to-controller and local interface. Intel® Quartus® Prime timing issues should always be evaluated and corrected before proceeding to any hardware testing.
PCB timing issues are usually Intel® Quartus® Prime timing issues, which are not reported in the Intel® Quartus® Prime software, if incorrect or insufficient PCB topology and layout information is not supplied. PCB timing issues are typically characterized by calibration failure, or failures during user mode when the hardware is heated or cooled. Further PCB timing issues are typically hidden if the interface frequency is lowered.
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