External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents General Guidelines

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Intel® Stratix® 10 devices, whether you are using the hard memory controller or your own solution.

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nd_version number/<synth|sim>/<variation_name>_altera_emif_arch_nd_version number_<unique ID>_readme.txt file, which is generated with your IP.

  1. EMIF IP pin-out requirements for the Intel® Stratix® 10 Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Intel® Quartus® Prime IP file (.qip), based on the IP configuration. When targeting Intel® Stratix® 10 HPS, you do not need to make location assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the Intel® Quartus® Prime software. Alternatively, consult the device handbook or the device pin-out files. For information on how you can customize the HPS EMIF pin-out, refer to Restrictions on I/O Bank Usage for Intel® Stratix® 10 EMIF IP with HPS .
  2. Ping Pong PHY, PHY only, RLDRAMx , and QDRx are not supported with HPS.

Observe the following general guidelines when placing pins for your Intel® Stratix® 10 external memory interface:

  1. Ensure that the pins of a single external memory interface reside within a single I/O column.
  2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
  3. Any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
  4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
  5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
  6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Intel® Stratix® 10 External Memory Interface Pin Information File, which is available on www.altera.com.

    You do not have to place every address and