External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents

13.7.4.3. Communicating Directly to the Legacy Efficiency Monitor and Protocol Checker

When you export the Legacy Efficiency Monitor, a CSR Avalon® slave interface is added to enable communication directly to the Efficiency Monitor and Protocol Checker without using the EMIF Debug Toolkit. You can create user logic to retrieve the efficiency statistic of the interface. The following table lists the memory map of the registers inside the Legacy Efficiency Monitor and Protocol Checker.

Before reading data in the CSR, you must issue a read command to address 0x01 to take a snapshot of the current data.

Table 354.  Avalon CSR Slave and JTAG Memory Map
Address Bit Name Default Access Description
0x01 31:0 Reserved 0 Read Only Used internally by the EMIF Debug Toolkit to identify Efficiency Monitor type. This address must be read prior to reading the other CSR contents.
0x02 31:0 Reserved Used internally by the EMIF Debug Toolkit to identify Efficiency Monitor version.
0x08 0   Write Only Write a 0 to reset.
7:1 Reserved Reserved for future use.
8   Write Only Write a 0 to reset.
15:9 Reserved Reserved for future use.
16   Read/Write Starting and stopping statistics gathering.
23:17 Reserved Reserved for future use.
31:24 Efficiency Monitor Status Read Only
  • bit 0: Efficiency Monitor stopped
  • bit 1: Waiting for start of pattern
  • bit 2: Running
  • bit 3: Counter saturation
0x10 15:0 Efficiency Monitor address width Read Only Address width of the Efficiency Monitor.
31:16 Efficiency Monitor data width Read Only Data width of the Efficiency Monitor.
0x11 15:0 Efficiency Monitor byte enable Read Only Byte enable width of the Efficiency Monitor.
31:16 Efficiency Monitor burst count width Read Only Burst count width of the Efficiency Monitor.
0x14 31:0 Cycle counter