11.1.1. Timing Analysis
Your Intel® Stratix® 10 EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.
Two timing analysis flows are available for Intel® Stratix® 10 EMIF IP:
- Early I/O Timing Analysis, which is a precompilation flow.
- Full Timing Analysis, which is a post-compilation flow.