External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents mem for DDR3

Interface between FPGA and external memory

Table 21.  Interface: memInterface type: Conduit
Port Name Direction Description
mem_ck Output CK clock
mem_ck_n Output CK clock (negative leg)
mem_a Output Address
mem_ba Output Bank address
mem_cke Output Clock enable
mem_cs_n Output Chip select
mem_rm Output Rank multiplication for LRDIMM. Typically, mem_rm[0] and mem_rm[1] connect to CS2# and CS3# of the memory buffer of all LRDIMM slots.
mem_odt Output On-die termination
mem_ras_n Output RAS command
mem_cas_n Output CAS command
mem_we_n Output WE command
mem_reset_n Output Asynchronous reset
mem_par Output Command and address parity
mem_dm Output Write data mask
mem_dq Bidirectional Read/write data
mem_dqs Bidirectional Data strobe
mem_dqs_n Bidirectional Data strobe (negative leg)
mem_alert_n Input Alert flag