9.4.1. QDR-IV Layout Approach
The following flowchart illustrates the recommended process to follow during the design phase, to determine timing margin and make iterative improvements to your design.
For more detailed simulation guidance, refer to the wiki: https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201
For information on intersymbol interference and crosstalk, refer to the wiki: https://community.intel.com/t5/FPGA-Wiki/Measuring-Channel-Signal-Integrity/ta-p/735495
For information on calculating board skew parameters, refer to Board Skew Equations, in this chapter.
If you know the absolute delays for all the memory related traces, the interactive Board Skew Parameter Tool can help you calculate the necessary parameters.
Memory Timing Parameters
You can find the memory timing parameters to enter in the parameter editor, in your memory vendor's datasheet.
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