External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents clks_sharing_slave_out for RLDRAM 3

Core clocks sharing slave output interface

Table 160.  Interface: clks_sharing_slave_outInterface type: Conduit
Port Name Direction Description
clks_sharing_slave_out Output This port may be used to fanout to another core clocks sharing slave. Alternatively, the master can fanout to all slaves.

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