External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
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11.1.1.2.1. Read Capture

Read capture timing analysis indicates the amount of slack on the DQ signals that are latched by the FPGA using the DQS strobe output of the memory device.

The Timing Analyzer analyzes read capture timing paths through conventional static timing analysis and further processing steps that account for memory calibration (which may include pessimism removal) and calibration uncertainties as shown in the following figure.

Figure 88. Read Capture Timing Analysis

Stratix 10 Read capture