External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents

6.3.1. Equations for DDR3 Board Skew Parameters

Table 207.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to DIMM/device The delay of the longest CK trace from the FPGA to any DIMM/device.
Where n is the number of memory clock and r is the number rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in each rank DIMM, the maximum CK delay is expressed by the following equation: