External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents Back-to-Back User-Controlled Refresh Usage

The following diagram illustrates the user-controlled refresh for the hard memory controller (HMC), using the MMR interface.
Figure 107. User-Controlled Refresh via MMR Interface

To perform a user-controlled refresh in the hard memory controller using the MMR interface, follow these steps:

  1. Write to the cfg_user_rfsh_en register (address=0x019) with the data 0x0000_0010 to enable user refresh.
  2. Write to the mmr_refresh_req register (address=0x02c) with the data 0x0000_0001 to send a refresh request to rank 0.
    • Each bit corresponds to one specific rank; for example, data 0x0000_0002 corresponds to rank 1.
    • You may program refreshes to more than one rank at a time.
  3. Read from the mmr_refresh_ack register (address=0x032) until the readdatavalid signal is asserted and the read data is 1'b1, indicating that a refresh operation is in progress.
  4. You can issue the next refresh request only after you see the acknowledge signal asserted (at time 4).
  5. Write to the mmr_refresh_req register (address=0x02c) with data 0x0000_0000 to disable the refresh request.
  6. You can implement a timer to track tRFC before sending the next user-controlled refresh.