External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents

13.9.6. Traffic Generator Status

The traffic generator reports its status in two ways: ISSPs and configuration interface.

Status Registers

The traffic generator reports status in two ways:

  • ISSPs
  • Configuration interface

Reading PNF Registers or ISSPs

The Pass Not Fail (PNF) registers show the status for each bit that has been read on the ctrl_amm interface.

pnf[x] = ~(amm_readdata_0[x]^amm_expected_readdata_0[x])

The PNF signal is “sticky”, which means that once a PNF bit is set to 0 due to a read miscompare, it does not return to a value of 1 on any consecutive reads, until the PNF is cleared. The PNF, TG_FAIL_EXPECTED_DATA, and TG_FAIL_READ_DATA registers are normally wider than a single register on the tg_cfg interface. As a result, the bus width is split up across NPNF_reg registers, where:

NPNF_reg = ceil(TG_RDATA_WIDTH / 32)

To determine the address of the Nth register:

TG_PNF[NPNF_reg] = (Symbol Address of TG_PNF) + 4*NPNF_reg

The maximum PNF width is 511 bits, so the bus width is split up across NPNF_ISSP ISSPs:


PNF ISSPs have the index in their name, starting with PNF0.


This example assumes the following conditions:

  • DQ Width: x72 (without ECC enabled)
  • Memory Protocol: DDR4
  • DQ/DQS: 8
  • Rate: Quarter-rate

Due to the memory protocol and rate, TG_DATA_RATE_WIDTH_RATIO = 8.

Therefore TG_RDATA_WIDTH = 72 * 8 = 576. This means that there are 18 TG_PNF registers, and two PNF ISSPs (PNF0, PNF1), as illustrated below:

Clearing Failure Information Between Runs

You can set the TG_CLEAR register to clear failure information between success