External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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6.4.3.2. x4 DIMM Implementation

DIMMS using a x4 DQS configuration require remapping of the DQS signals to achieve compatibility between the EMIF IP and the JEDEC standard DIMM socket connections.

The necessary remapping is shown in the table below. You can implement this DQS remapping in either RTL logic or in your schematic wiring connections.

Table 209.  Mapping of DQS Signals Between DIMM and the EMIF IP
DIMM   Intel® Quartus® Prime EMIF IP
DQS0 DQ[3:0]   DQS0 DQ[3:0]
DQS9 DQ[7:4]   DQS1 DQ[7:4]
DQS1 DQ[11:8]   DQS2 DQ[11:8]
DQS10 DQ[15:12]   DQS3 DQ[15:12]
DQS2 DQ[19:16]   DQS4 DQ[19:16]
DQS11 DQ[23:20]