External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents x4 DIMM Implementation

DIMMS using a x4 DQS configuration require remapping of the DQS signals to achieve compatibility between the EMIF IP and the JEDEC standard DIMM socket connections.

The necessary remapping is shown in the table below. You can implement this DQS remapping in either RTL logic or in your schematic wiring connections.

Table 209.  Mapping of DQS Signals Between DIMM and the EMIF IP
DIMM   Intel® Quartus® Prime EMIF IP
DQS0 DQ[3:0]   DQS0 DQ[3:0]
DQS9 DQ[7:4]   DQS1 DQ[7:4]
DQS1 DQ[11:8]   DQS2 DQ[11:8]
DQS10 DQ[15:12]   DQS3 DQ[15:12]
DQS2 DQ[19:16]   DQS4 DQ[19:16]
DQS11 DQ[23:20]   DQS5 DQ[23:20]
DQS3 DQ[27:24]   DQS6 DQ[27:24]
DQS12 DQ[31:28]   DQS7 DQ[31:28]
DQS4 DQ[35:32]   DQS8 DQ[35:32]
DQS13 DQ[39:36]   DQS9 DQ[39:36]
DQS5 DQ[43:40]   DQS10 DQ[43:40]
DQS14 DQ[47:44]   DQS11 DQ[47:44]
DQS6 DQ[51:48]   DQS12 DQ[51:48]
DQS15 DQ[55:52]   DQS13 DQ[55:52]
DQS7 DQ[59:56]   DQS14 DQ[59:56]
DQS16 DQ[63:60]   DQS15 DQ[63:60]
DQS8 DQ[67:64]   DQS16 DQ[67:64]
DQS17 DQ[71:68]   DQS17 DQ[71:68]

Data Bus Connection Mapping Flow

  1. Connect all FPGA DQ pins accordingly to DIMM DQ pins. No remapping is required.
  2. DQS/DQSn remapping is required either on the board schematics or in the RTL code.
  3. An example mapping is shown below, with reference to the above table values:
    FPGA (DQS0) to DIMM (DQS0)
    FPGA (DQS1) to DIMM (DQS9)
    FPGA (DQS2) to DIMM (DQS1)
    FPGA (DQS16) to DIMM (DQS8)
    FPGA (DQS17) to DIMM (DQS17)

When designing a board to support x4 DQS groups, Intel® recommends that you make it compatible for x8 mode, for the following reasons:

  • Provides the flexibility of x4 and x8 DIMM support.
  • Allows use of x8 DQS group connectivity rules.
  • Allows use of x8 timing rules for matching. Intel® strongly recommends adhering to x4/x8 interoperability rules when designing a DIMM interface, even if the primary use case is to support x4 DIMMs only, because doing so facilitates debug and future migration capabilities. Regardless, the rules for length matching for two nibbles in a x4 interface must match those of the signals for a corresponding x8 interface, as the data terminations are turned on and off at the same time for both x4 DQS groups in an I/O lane. If the two x4 DQS groups were to have significantly different trace delays, it could adversely affect signal integrity.

About Pinout and Schematic Reviewing

When viewing x4 DQS mode in the Pin Planner, the 4 DQ pins do not have to be placed in the same colour-coded x4 group with the associated DQS/DQSn pins. This might look odd, but is not incorrect. The x4 DQS pins can be used as the strobe for any DQ pins placed within a x8 DQS group in an I/O lane.

Necessary checks to perform if the DQS groups are remapped in the RTL code

  1. In the Pin Planner, view x8 DQS groups and check the following: