External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Document Table of Contents
Give Feedback emif_usr_clk_sec for DDR3

User clock interface (for the secondary interface in ping-pong configuration)

Table 30.  Interface: emif_usr_clk_secInterface type: Clock Output
Port Name Direction Description
emif_usr_clk_sec Output User clock domain. Intended for the secondary interface in a ping-pong configuration.