External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents Efficiency Monitor Block Descriptions

The Efficiency Monitor accepts Avalon® signals from a master and sends commands downstream to a slave without modifying anything on the interface.
Figure 162. Sample Efficiency Monitor Topology

amm_emif interface

The Efficiency Monitor passes traffic downstream to the external memory interface on this interface.

amm_user interface

The traffic generator (or custom user logic) initiates traffic and passes it to the Efficiency Monitor over this interface.

effmon_csr interface

This interface consists of several configuration and status registers. The Efficiency Monitor Mode parameter controls whether this interface is exported for you to provide a custom master, or connected internally so that the System Console can act as master on this interface.