External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents

4.1.2.19. emif_usr_reset_n_sec for DDR4

User clock domain reset interface (for the secondary interface in ping-pong configuration)

Table 67.  Interface: emif_usr_reset_n_secInterface type: Reset Output
Port Name Direction Description
emif_usr_reset_n_sec Output Reset for the user clock domain. Asynchronous assertion and synchronous deassertion. Intended for the secondary interface in a ping-pong configuration.