External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022

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Document Table of Contents OCT

You require one OCT calibration block if you are using an FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design. You can select any available OCT calibration block—it need not be within the same bank or side of the device as the memory interface pins. The only requirement is that the I/O bank where you place the OCT calibration block must use the same VCCIO voltage as the memory interface.

The OCT calibration block uses a single RZQ pin. The RZQ pin in Intel® Stratix® 10 devices can be used as a general purpose I/O pin when it is not used to support OCT, provided the signal conforms to the bank voltage requirements.