External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents

9.3.1.6.1. General Guidelines

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Intel® Stratix® 10 devices, whether you are using the hard memory controller or your own solution.

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nd_version number/<synth|sim>/<variation_name>_altera_emif_arch_nd_version number_<unique ID>_readme.txt file, which is generated with your IP.

Note:
  1. EMIF IP pin-out requirements for the Intel® Stratix® 10 Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Intel® Quartus® Prime IP file (.qip), based on the IP configuration. When targeting Intel® Stratix® 10 HPS, you do not need to make location assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the Intel® Quartus® Prime software. Alternatively, consult the device handbook or the device pin-out files. For information on how you can customize the HPS EMIF pin-out, refer to Restriction