External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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13.9.9. Examples of Configuring the TG2 Traffic Generator

Example 1: Configuring TG2 to Write and Read from All Memory Locations with Alternating 0x555_5555_5555_5555 and 0xAAA_AAAA_AAAA_AAAA Data Pattern

In this example, 227 logical addresses are available on the EMIF controller. This example is a x72 DDR4 interface, configured to use Quarter Rate (QR) user logic.

Figure 210. Address Width for Memory IP

To write to all memory locations for a memory IP, starting from address=0x0 , it is necessary to satisfy the following requirement:

TG_LOOP_COUNT x TG_BURST_LENGTH x TG_WRITE_COUNT = Total Logical Address Available

For this example, assume the following:

  • TG_BURST_LENGTH = 64 (in decimal) or TG_BURST_LENGTH = 0x40 (in hexadecimal).
  • TG_WRITE_COUNT = 1.

You can calculate the required TG_LOOP_COUNT as follows:

TG_LOOP_COUNT = Total Logical Address Available / (TG_WRITE_COUNT x TG_BURST_LENGTH)
= 227/64
= 2097152 (in decimal)
= 0x20_0000 (in hexadecimal)

To configure the TG2 using core logic, follow these steps:

  1. Write to TG_CLEAR with data=0xF to clear all the failure status registers.
  2. Configure the registers with the value specified in table 1 below.
  3. Write to TG_START to start the TG2 using the configuration in step 2. This starts the traffic test in user mode.
  4. Read from TG_TEST_COMPLETE until the read data =0x1, indicating the traffic test has completed.
  5. Read from TG_PASS, TG_FAIL, and TG_TIMEOUT to check the test result.
    • TG_PASS. A value of 1 indicates that the traffic test passed at the end of all test stages.
    • TG_FAIL. A value of 1 indicates that the configured traffic finished running but a failure (read miscompare) was observed. You may read from other relevant registers to get more information about the failure. Refer to the Configuration and Status Registers table for information on the available registers.
    • TG_TIMEOUT. A value of 1 indicates that a read response was not received from the interface for one or more read commands.
Table 366.  TG2 Configuration to Write and Read from All Memory Locations in Example 1
Address Register Name Value Remarks
0x8 TG_LOOP_COUNT 0x20_0000 Require 2097152* 64 to cover all memory locations.
0xC TG_WRITE_COUNT 0x1  
0x10 TG_READ_COUNT 0x1  
0x14 TG_WRITE_REPEAT_COUNT 0x1  
0x18 TG_READ_REPEAT_COUNT 0x1  
0x1C TG_BURST_LENGTH 0x40 Require 2097152* 64 to cover all memory locations.
0x38 TG_RW_GEN_IDLE_COUNT 0x1  
0x3C TG_RW_GEN_LOOP_IDLE_COUNT 0x1  
0x40 TG_SEQ_START_ADDR_WR_L 0x0 Lower 32-bit of start write address.