External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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Document Table of Contents

15. Document Revision History for External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.26 22.3 19.2.5 In the Using the Configurable Traffic Generator (TG2) section of the Debugging chapter, added the Claiming and Releasing the TG Config Interface topic.
2022.03.11 21.3 19.2.4 In the Debugging Intel® Stratix® 10 EMIF IP section of the Debugging chapter, added Guidelines for Debugging Calibration Issues section.
2021.12.06 21.3 19.2.4
  • Removed the Multiple Interfaces in the Same I/O Column paragraph from the General Guidelines topic in the Pin Guidelines section of each protocol-specific chapter.
  • In the DDR4 chapter:
    • Added the alert_n Pin Termination Recommendation topic to the Pin Guidelines section.
    • Modified the alert_n pin termination recommendation in the Length Matching Rules topic.
2021.10.04 21.3 19.2.4
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR3 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the DDR4 chapter:
    • Added the Register Map IP-XACT Support for Intel® Stratix® 10 EMIF DDR3 IP topic.
  • In the Debugging chapter: