External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public
Document Table of Contents

4.1.1.22. cal_debug_out_reset_n for DDR3

User calibration debug clock domain reset interface

Table 33.  Interface: cal_debug_out_reset_nInterface type: Reset Output
Port Name Direction Description
cal_debug_out_reset_n Output Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion