External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

13.7.2. Debugging with the External Memory Interface Unified Calibration Debug Toolkit

The External Memory Interface Unified Calibration Debug Toolkit for Stratix® 10 FPGAs provides access to data collected by the sequencer during memory calibration, and provides analysis tools for evaluating the calibrated interface stability and assessing hardware conditions.

The toolkit provides the following reports:

  • Interface and memory configuration, such as external memory protocol and interface width.
  • Calibration results including status (pass/fail), failure stage (if applicable), delay settings and margins, VREF settings and margins.

The available tasks and analysis tools enable the following:

  • Requesting recalibration of the memory interface.
  • Reading the probe data or writing the source data to the In-System Sources and Probes (ISSPs) instances in the design.
  • Viewing the delay setting on any pin in the selected interface and updating it if necessary.
  • Rerunning the traffic generator in the example design.
  • Running VREF Margining on the interface.
  • Running Driver Margining on the interface.
  • Calibrating or update the termination settings.