External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

15. Document Revision History for External Memory Interfaces Stratix® 10 FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.04.01 24.1 19.2.8
  • In each of the protocol-specific chapters, removed references to the Use Soft NIOS Processor for On-Chip Debug parameter.
  • In the Debug chapter, removed a sentence from the EMIF On-Chip Debug Port topic.
2022.09.26 22.3 19.2.5 In the Using the Configurable Traffic Generator (TG2) section of the Debugging chapter, added the Claiming and Releasing the TG Config Interface topic.
2022.03.11 21.3 19.2.4 In the Debugging Stratix® 10 EMIF IP section of the Debugging chapter, added Guidelines for Debugging Calibration Issues section.
2021.12.06 21.3 19.2.4
  • Removed the Multiple Interfaces in the Same I/O Column paragraph from the General Guidelines topic in the Pin Guidelines section of each protocol-specific chapter.
  • In the DDR4 chapter:
    • Added the alert_n Pin Termination Recommendation topic to the Pin Guidelines section.
    • Modified the alert_n pin termination recommendation in the Length Matching Rules topic.
2021.10.04 21.3 19.2.4
  • In the Simulating chapter, changed Mentor Graphics to Siemens EDA, and ModelSim - Intel FPGA Edition to Questa - Intel FPGA Edition.
  • In the DDR3 chapter:
    • Added the Register Map IP-XACT Support for Stratix® 10 EMIF DDR3 IP topic.
  • In the DDR4 chapter:
    • Added the Register Map IP-XACT Support for Stratix® 10 EMIF DDR3 IP topic.
  • In the Debugging chapter:
    • Updated the Configuration and Status Registers table.
    • Updated the Address Pattern topic.
    • Updated the Address Pattern topic and added several new topics:
      • Address Generator Modes
      • Address Generator MSB Indices
      • Address Generator Effective Width
      • Address Generator Relative Frequencies
      • Address Pattern Examples - Basic Mode
      • Address Pattern Examples - Advanced Mode
    • Updated the Error Codes table.
    • In the Configuring the Traffic Generator topic, updated the Configurations Tab figure, and added several figures:
      • Instruction Pattern tab: Separate Read and Write Settings
      • Address Pattern Tab – Basic Mode
      • Address Pattern Tab – Advanced Mode
      • Address Pattern tab: Separate Read and Write Settings – Basic Mode
      • Address Pattern tab: Separate Read and Write Settings – Advanced Mode
2021.07.09 21.2 19.2.4 In the Debugging chapter, modified the Code Value column, and added one row, to the Error Codes table in the Traffic Generator Status topic. .
2021.06.21 21.2 19.2.4
  • In the Simulation chapter, added information to the Skip Calibration Mode description in the Calibration Modes topic.
  • In the Debugging chapter, added the Examples of Configuring the TG2 Traffic Generator topic in the Using the Configurable Traffic Generator (TG2) section.
2021.03.29 21.1 19.2.3
  • In the Simulating Memory IP chapter, removed references to the NCSim* simulator.
  • In the Stratix® 10 EMIF IP DDR4 chapter, added content to the Enable ALERT#/PAR pins description, in the Stratix® 10 EMIF IP DDR4 Parameters: Memory topic.
  • Added Package Migration topic to the Board Design Guidelines section of each protocol-specific chapter.
2020.12.18 20.4 19.2.2
  • In the Simulation chapter, added a paragraph to the Simulation Walkthrough topic.
  • In the Debugging chapter, removed the Using the Traffic Generator with the Generated Design Example topic, and added the Using the Default Traffic Generator and Using the Configurable Traffic Generator (TG2) sections.
2020.10.05 20.3 19.2.2
  • In the Introduction chapter, updated the Release Information topic.
  • In the MMR Tables section of the End-User Signals chapter, added ECC error information to the ecc6: Address of Most Recent Correction Command Dropped topic.
  • In the Debugging chapter, renamed the existing EMIF Debug Toolkit as the Legacy EMIF Debug Toolkit.
  • In the Unified Calibration Debug Toolkit section of the Debugging chapter, modified the following topics:
    • Adding Interfaces to a Design Example (updated images)
    • Calibration Tab (updated images and added section on changing address ordering)
    • Calibration Report Tab (added ODT Settings in Effect section, modified Calibration Status Report section, and added Address and Command Calibration Delays and Margins section)
    • Calibrate Termination Tab (recast text, updated images, added ODT Assertion Table section)
    • ISSP Tab (added PRTY description to Table 351)
    • Viewing Diagrams in the Eye Viewer (added a fourth eye diagram)
  • In the Legacy Efficiency Monitor and Protocol Checker section, made minor changes to several topics to differentiate between the legacy efficiency monitor and the new efficiency monitor.
  • Added the New Efficiency Monitor section, consisting of the following topics:
    • New Efficiency Monitor
    • Enabling the Efficiency Monitor in a Design Example
    • Efficiency Monitor Block Descriptions
    • Control and Status Registers
    • Opening the Efficiency Monitor
2020.06.22 20.2 19.2.1
  • In the Functional Simulation chapter, added a third note to the Abstract PHY Simulation topic.
  • In the Debugging chapter:
    • Added content to the Debugging Stratix® 10 EMIF IP topic.
    • Added the Debugging with the External Memory Interface Unified Calibration Debug Toolkit section.
2020.04.30 20.1 19.2.0
  • In the Interface and Signal Descriptions chapter, added ctrl_ecc_status_for DDR3 and ctrl_ecc_status_for_DDR4 topics.
2020.04.10