External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

13.8.3. Changing the Reset Trigger of the Default Traffic Generator

As generated, the design example project responds to an active-high reset pulse on the local_reset_req signal.

If you prefer to have a level-sensitive, typically active-low reset signal as was common with earlier device families, you can invert the design example reset signal by making the following RTL changes to the ed_synth.v file:

  • Add the following two lines in the wire declaration section:
    wire reset_invert;
    assign reset_invert = !local_reset_req;
  • Where the reset block is instantiated, change the local_reset_req to connect to the inverted reset signal called reset_invert, as follows:
    ed_synth_local_reset_combiner local_reset_combiner (

In addition, it is a good idea — though not mandatory — to also run analysis and elaboration, to help show project structure and verify assignments.