External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

13.9.5.2.6. Address Pattern Examples - Advanced Mode

The examples in this topic include the generated address on both the Avalon® address (amm_address_0) and the memory address (mem_addr).

The difference in widths between amm_address_0 and mem_addr is based on the configured EMIF IP variant.

The following points apply to the examples that follow:

  • A value of X indicates that a register is not used, making its value irrelevant.
  • The address width (31) is the SYMBOL ADDRESS, as output from the traffic generator. In the design used for these examples, the AMM_WORD_ADDRESS_WIDTH is 26 bits. To account for this difference, the traffic generator shifts all addresses by the difference (5 bits). The examples below use this shifted address, but the external memory interface does not see this shift on its side of the ctrl_amm interface.
  • The provided waveform is only a snippet of the full instruction pattern, to demonstrate the write instructions and the corresponding addresses. Not all read blocks are shown, due to space restrictions.

The width of the Avalon® address is based on the following:

  • The data width on the memory side.
  • Whether a configured EMIF IP is quarter rate, half rate, or full rate.
  • Whether the memory interface is double data rate or quarter data rate.

Example 1: Random Address Mode

Consider the following instruction pattern:

TG_LOOP_COUNT=2 TG_WRITE_REPEAT_COUNT=1 TG_RW_GEN_IDLE_COUNT=2
TG_WRITE_COUNT=3 TG_READ_REPEAT_COUNT=1 TG_RW_GEN_LOOP_IDLE_COUNT=0
TG_READ_COUNT=3 TG_BURST_LENGTH=1
Table 359.  Address Pattern
   
Write Start Addresses:
TG_SEQ_START_ADDR_WR  =0x5a5a
TG_SEQ_START_ADDR_WR+1=0x0000
TG_SEQ_START_ADDR_WR+2=X
       …
TG_SEQ_START_ADDR_WR+11=X
Read Start Addresses:
TG_SEQ_START_ADDR_RD  =0x5a5a
TG_SEQ_START_ADDR_RD+1=0x0000
TG_SEQ_START_ADDR_RD+2=X
       …
TG_SEQ_START_ADDR_RD+11=X
Write Address Modes:
TG_ADDR_MODE_WR=1
TG_ADDR_MODE_WR+1=3
       …
TG_ADDR_MODE_WR+5=3
Read Address Modes:
TG_ADDR_MODE_RD=1
TG_ADDR_MODE_RD+1=3
       …
TG_ADDR_MODE_RD+5=3
Sequential Address Increments:
TG_SEQ_ADDR_INCR=X
TG_SEQ_ADDR_INCR+1=X
       …
TG_SEQ_ADDR_INCR+5=X
Return to Start Address:
TG_RETURN_TO_START_ADDR=0
Relative Frequencies:
TG_ADDR_FIELD_RELATIVE_FREQ=1
TG_ADDR_FIELD_RELATIVE_FREQ+1=X
       …
TG_ADDR_FIELD_RELATIVE_FREQ+5=X
MSB Indices:
TG_ADDR_FIELD_MSB_INDEX=AMM_WORD_ADDRESS_WIDTH-1
TG_ADDR_FIELD_MSB_INDEX+1=X
       …
TG_ADDR_FIELD_MSB_INDEX+4=X
Figure 180. Setting the Address Pattern in the Traffic Generator Configuration Interface

Figure 181. Random Address Mode

Example 2: Sequential Address Mode

Consider the following instruction pattern:

TG_LOOP_COUNT=2 TG_WRITE_REPEAT_COUNT=1 TG_RW_GEN_IDLE_COUNT=0
TG_WRITE_COUNT=3 TG_READ_REPEAT_COUNT=1 TG_RW_GEN_LOOP_IDLE_COUNT=1
TG_READ_COUNT=3 TG_BURST_LENGTH=1

Table 360.  Address Pattern
   
Write Start Addresses:
TG_SEQ_START_ADDR_WR  =’0
TG_SEQ_START_ADDR_WR+1=’0
TG_SEQ_START_ADDR_WR+2=X
       …
TG_SEQ_START_ADDR_WR+11=X
Read Start Addresses:
TG_SEQ_START_ADDR_RD  =’0 
TG_SEQ_START_ADDR_RD+1=’0
TG_SEQ_START_ADDR_RD+2=X
       …
TG_SEQ_START_ADDR_RD+11=X
Write Address Modes:
TG_ADDR_MODE_WR=2
TG_ADDR_MODE_WR+1=3
       …
TG_ADDR_MODE_WR+5=3
Read Address Modes:
TG_ADDR_MODE_RD=2
TG_ADDR_MODE_RD+1=3
       …
TG_ADDR_MODE_RD+5=3
Sequential Address Increments:
TG_SEQ_ADDR_INCR=8
TG_SEQ_ADDR_INCR+1=X
       …
TG_SEQ_ADDR_INCR+5=X
Return to Start Address:
TG_RETURN_TO_START_ADDR=0
Relative Frequencies:
TG_ADDR_FIELD_RELATIVE_FREQ=1
TG_ADDR_FIELD_RELATIVE_FREQ+1=X
       …
TG_ADDR_FIELD_RELATIVE_FREQ+5=X
MSB Indices:
TG_ADDR_FIELD_MSB_INDEX=AMM_WORD_ADDRESS_WIDTH-1
TG_ADDR_FIELD_MSB_INDEX+1=X
       …
TG_ADDR_FIELD_MSB_INDEX+4=X
Figure 182. Sequential Address Mode

Example 3: Sequential Address Mode with TG_RETURN_TO_START_ADDR_1

Consider the following instruction pattern:

TG_LOOP_COUNT=2 TG_WRITE_REPEAT_COUNT=1 TG_RW_GEN_IDLE_COUNT=0
TG_WRITE_COUNT=3 TG_READ_REPEAT_COUNT=1 TG_RW_GEN_LOOP_IDLE_COUNT=1
TG_READ_COUNT=3 TG_BURST_LENGTH=1

Table 361.  Address Pattern
Write Start Addresses:
TG_SEQ_START_ADDR_WR  =’0
TG_SEQ_START_ADDR_WR+1=’0
TG_SEQ_START_ADDR_WR+2=X
       …
TG_SEQ_START_ADDR_WR+11=X
Read Start Addresses:
TG_SEQ_START_ADDR_RD  =’0 
TG_SEQ_START_ADDR_RD+1=’0
TG_SEQ_START_ADDR_RD+2=X
       …
TG_SEQ_START_ADDR_RD+11=X
Write Address Modes:
TG_ADDR_MODE_WR=2
TG_ADDR_MODE_WR+1=3
       …
TG_ADDR_MODE_WR+5=3
Read Address Modes:
TG_ADDR_MODE_RD=2
TG_ADDR_MODE_RD+1=3
       …
TG_ADDR_MODE_RD+5=3
Sequential Address Increments:
TG_SEQ_ADDR_INCR=8
TG_SEQ_ADDR_INCR+1=X
       …
TG_SEQ_ADDR_INCR+5=X
Return to Start Address:
TG_RETURN_TO_START_ADDR=1
Relative Frequencies:
TG_ADDR_FIELD_RELATIVE_FREQ=1
TG_ADDR_FIELD_RELATIVE_FREQ+1=X
       …
TG_ADDR_FIELD_RELATIVE_FREQ+5=X
MSB Indices:
TG_ADDR_FIELD_MSB_INDEX+1=AMM_WORD_ADDRESS_WIDTH-1
TG_ADDR_FIELD_MSB_INDEX+1=X
       …
TG_ADDR_FIELD_MSB_INDEX+4=X
Figure 183. Setting the Address Pattern in the Traffic Generator Configuration Interface

Figure 184.  Sequential Address Mode with TG_RETURN_TO_START_ADDR=1

Example 4: Random Sequential Address Mode

Consider the following instruction pattern:

TG_LOOP_COUNT=1 TG_WRITE_REPEAT_COUNT=1 TG_RW_GEN_IDLE_COUNT=1
TG_WRITE_COUNT=8 TG_READ_REPEAT_COUNT=1 TG_RW_GEN_LOOP_IDLE_COUNT=1
TG_READ_COUNT=8 TG_BURST_LENGTH=1

Table 362.  Address Pattern
Write Start Addresses:
TG_SEQ_START_ADDR_WR  =0x0000
TG_SEQ_START_ADDR_WR+1=0x0000
TG_SEQ_START_ADDR_WR+2=0xaaaa
TG_SEQ_START_ADDR_WR+3=0x0000
TG_SEQ_START_ADDR_WR+4=X
       …
TG_SEQ_START_ADDR_WR+11=X
Read Start Addresses:
TG_SEQ_START_ADDR_RD  =0x0000
TG_SEQ_START_ADDR_RD+1=0x0000
TG_SEQ_START_ADDR_RD+2=0xaaaa
TG_SEQ_START_ADDR_RD+3=0x0000
TG_SEQ_START_ADDR_RD+4=X
       …
TG_SEQ_START_ADDR_RD+11=X
Write Address Modes:
TG_ADDR_MODE_WR=2
TG_ADDR_MODE_WR+1=1
TG_ADDR_MODE_WR+2=3
       …
TG_ADDR_MODE_WR+5=3
Read Address Modes:
TG_ADDR_MODE_RD=2
TG_ADDR_MODE_RD+1=1
TG_ADDR_MODE_RD+2=3
       …
TG_ADDR_MODE_RD+5=3
Sequential Address Increments:
TG_SEQ_ADDR_INCR=2
TG_SEQ_ADDR_INCR+1=X
       …
TG_SEQ_ADDR_INCR+5=X
Return to Start Address:
TG_RETURN_TO_START_ADDR=0
Relative Frequencies:
TG_ADDR_FIELD_RELATIVE_FREQ=1
TG_ADDR_FIELD_RELATIVE_FREQ+1=4
TG_ADDR_FIELD_RELATIVE_FREQ+2=X
TG_ADDR_FIELD_RELATIVE_FREQ+3=X
TG_ADDR_FIELD_RELATIVE_FREQ+4=X
TG_ADDR_FIELD_RELATIVE_FREQ+5=X
MSB Indices:
TG_ADDR_FIELD_MSB_INDEX=3
TG_ADDR_FIELD_MSB_INDEX+1=AMM_WORD_ADDRESS_WIDTH-1
TG_ADDR_FIELD_MSB_INDEX+4=X
TG_ADDR_FIELD_MSB_INDEX+4=X
TG_ADDR_FIELD_MSB_INDEX+4=X
Figure 185. Setting the Address Pattern in the Traffic Generator Configuration Interface
Figure 186.  Random-Sequential Address Mode