External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

8.1.2. Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory

Table 264.  Group: Memory / Topology
Display Name Description
Data width per device Number of D and Q pins per QDR II device. (Identifier: MEM_QDR2_DATA_PER_DEVICE)
Enable BWS# pins Indicates whether the interface uses the BWS#(Byte Write Select) pins. If enabled, 1 BWS# pin for every 9 D pins will be added. (Identifier: MEM_QDR2_BWS_EN)
Enable width expansion Indicates whether to combine two memory devices to double the data bus width. With two devices, the interface supports a width expansion configuration up to 72-bits. For width expansion configuration, the address and control signals are routed to 2 devices. (Identifier: MEM_QDR2_WIDTH_EXPANDED)
Address width Number of address pins. (Identifier: MEM_QDR2_ADDR_WIDTH)
Burst length Burst length of the memory device. (Identifier: MEM_QDR2_BL)