External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents General Guidelines

You should follow the recommended guidelines when performing pin placement for all external memory interface pins targeting Stratix® 10 devices, whether you are using the hard memory controller or your own solution.

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nd_version number/<synth|sim>/<variation_name>_altera_emif_arch_nd_version number_<unique ID>_readme.txt file, which is generated with your IP.

  1. EMIF IP pin-out requirements for the Stratix® 10 Hard Processor Subsystem (HPS) are more restrictive than for a non-HPS memory interface. The HPS EMIF IP defines a fixed pin-out in the Quartus® Prime IP file (.qip), based on the IP configuration. When targeting Stratix® 10 HPS, you do not need to make location assignments for external memory interface pins. To obtain the HPS-specific external memory interface pin-out, compile the interface in the Quartus® Prime software. Alternatively, consult the device handbook or the device pin-out files. For information on how you can customize the HPS EMIF pin-out, refer to Restrictions on I/O Bank Usage for Stratix® 10 EMIF IP with HPS .
  2. Ping Pong PHY, PHY only, RLDRAMx, and QDRx are not supported with HPS.

Observe the following general guidelines when placing pins for your Stratix® 10 external memory interface:

  1. Ensure that the pins of a single external memory interface reside within a single I/O column.
  2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
  3. Any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
  4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
  5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
  6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Stratix® 10 External Memory Interface Pin Information File, which is available on www.altera.com.

    You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.

    Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<unique ID>_readme.txt file after you have generated your IP.
  7. An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
  8. An I/O lane must not be used by both address and command pins and data pins.
  9. Place read data groups according to the DQS grouping in the pin table and Pin Planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
    1. Unlike other device families, there is no need to swap CQ/CQ# pins in certain QDR II and QDR II+ latency configurations.
    2. QDR-IV requires that the polarity of all QKB/QKB# pins be swapped with respect to the polarity of the differential buffer inputs on the FPGA to ensure correct data capture on port B. All QKB pins on the memory device must be connected to the negative pins of the input buffers on the FPGA side, and all QKB# pins on the memory device must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
  10. You can implement two x4 DQS groups with a single I/O lane. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
    • There must be an even number of x4 groups in an external memory interface.
    • DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
    • When placing DQ pins in x4 mode, it is important to stay within an I/O lane when swapping pin locations. In other words, you may swap DQ pins within a given DQS group or across an adjacent DQS group, so long as you are within the same I/O lane. The following table illustrates an example, where DATA_A and DATA_B are swap groups, meaning that any pin in that index can move within that range of pins.
      Index Within Lane DQS x4 Locations
      11 DATA_B[3:0]
      10 DATA_B[3:0]
      9 DQS_Bn
      8 DQS_Bp
      7 DATA_B[3:0]
      6 DATA_B[3:0]
      5 DQS_An
      4 DQS_Ap
      3 DATA_A[3:0]
      2 DATA_A[3:0]
      1 DATA_A[3:0]
      0 DATA_A[3:0]
  11. You should place the write data groups according to the DQS grouping in the pin table and Pin Planner. Output-only data clocks for QDR II, QDR II+, and QDR II+ Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, but must be placed on a differential pin pair. They must be placed in the same I/O bank as the corresponding DQS group.
    Note: For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.
  12. For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.

    You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.

  13. Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.
  14. Be aware that for DDR4 interfaces clocked at 1333 MHz, total I/O bank usage is limited as follows:
    Package Total I/O 48 banks Maximum number of I/O 48 banks that can be used for 1333 MHz Remaining I/O 48 bank usage for EMIF or general-purpose I/O
    1760 14 12 Do not use.
    2397B 14 12 Do not use.
    2912E 24 20 Do not use.
  1. x4 mode does not support DM/DBI, or Stratix® 10 EMIF IP for HPS.
  2. If you are using an