External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents clks_sharing_master_out for QDR II/II+/II+ Xtreme

Core clocks sharing master interface

Table 104.  Interface: clks_sharing_master_outInterface type: Conduit
Port Name Direction Description
clks_sharing_master_out Output This port should fanout to all the core clocks sharing slaves.