External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

3.2. Stratix® 10 EMIF Sequencer

The Stratix® 10 EMIF sequencer is fully hardened in silicon, with executable code to handle protocols and topologies. Hardened RAM contains the calibration algorithm.

The Stratix® 10 EMIF sequencer is responsible for the following operations:

  • Initializes memory devices.
  • Calibrates the external memory interface.
  • Governs the hand-off of control to the memory controller.
  • Handles recalibration requests and debug requests.
  • Handles all supported protocols and configurations.
Figure 12.  Stratix® 10 EMIF Sequencer Operation