External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 11/28/2024
Public
Document Table of Contents

10.2.1. Equations for RLDRAM 3 Board Skew Parameters

Table 344.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to device The delay of the longest CK trace from the FPGA to any device.
where n is the number of memory clocks. For example, the maximum CK delay for two pairs of memory clocks is expressed by the following equation:
Maximum DK delay to device The delay of the longest DK trace from the FPGA to any device.
where n is the number of DK. For example, the maximum DK delay for two DK is expressed by the following equation: