External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

3.5.3. PLL Reference Clock Sharing

To implement PLL reference clock sharing, in your RTL code connect the PLL reference clock signal at your design's top-level to the PLL reference clock port of multiple interfaces.

To share a PLL reference clock, the following requirements must be met:

  • Interfaces must expect a reference clock signal of the same frequency.
  • Interfaces must be placed in the same column.
  • Interfaces must be placed at adjacent bank locations.