External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 11/28/2024
Public
Document Table of Contents

9.2.1. Equations for QDR-IV Board Skew Parameters

Table 315.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum system skew within address/command bus The largest skew between the address and command signals. Enter combined board and package skew.
Average delay difference between address/command and CK

The average delay difference between the address and command signals and the CK signal, calculated by averaging the longest and smallest Address/Command signal delay minus the CK delay. Positive values represent address and command signals that are longer than CK signals and negative values represent address and command signals that are shorter than CK signals. The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins.