External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 11/28/2024
Public
Document Table of Contents

8.2.1. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters

Table 284.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum system skew within address/command bus
The largest skew between the address and command signals. Enter combined board and package skew.
Average delay difference between address/command and K The average delay difference between the address and command signals and the K signal, calculated by averaging the longest and smallest Address/Command signal delay minus the K delay. Positive values represent address and command signals that are longer than K signals and negative values represent address and command signals that are shorter than K signals. The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins.