External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents Debugging VREFIN Calibration Failure

  1. Ensure that the VCCIO of the failing group is powered up to VCCIO=1.2V at the FPGA side.
  2. Regenerate the EMIF IP with other Initial VREFIN values. It defaults to 61% when using the default FPGA I/O settings.
    Figure 155. Changing the Initial VREFIN Value