External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Public
Document Table of Contents

13.9.4. Configuration and Status Registers

You can configure the user traffic pattern by writing to configuration registers that influence the resulting traffic pattern.

Configuration registers that govern the resulting traffic pattern affect one of the following aspects of the pattern:

  • Test duration / Instruction pattern
  • Address pattern
  • Data pattern
Note: This section describes the registers that configure a traffic pattern as seen on the ctrl_amm interface.
Table 358.  Configuration and Status Registers
Symbol Address Register Name Register Width Number of Registers Readable or Writeable Register Section Register Description
0x0 TG_VERSION 32 1 Readable N/A Version number of the traffic generator address map.
0x4 TG_START 1 1 Writeable N/A Perform a write to this register to start the traffic generator (any value).
0x8 TG_LOOP_COUNT 32 1 Readable and Writeable Test Duration/Instruction Pattern The number of read/write loops to run. A loop is defined as a block of writes followed by a block of reads.

If this value is set to 0, the traffic generator will run infinite loops.

0xC TG_WRITE_COUNT 12 1 Readable and Writeable Test Duration/Instruction Pattern The number of unique writes to perform in each loop.
0x10 TG_READ_COUNT 12 1 Readable and Writeable Test Duration/Instruction Pattern Number of unique reads to perform in each loop.
0x14 TG_WRITE_REPEAT_COUNT 16 1 Readable and Writeable Test Duration/Instruction Pattern Number of times to repeat each write operation.
0x18 TG_READ_REPEAT_COUNT 16 1 Readable and Writeable Test Duration/Instruction Pattern Number of times to repeat each read operation.
0x20 TG_CLEAR 4 1 Readable and Writeable Status Clears the failure status registers. Allows clearing these registers independently from one another by writing a 1 to the following bits.

BIT0 - Clears the recorded PNF data.

BIT1 - Clears the recorded number of Avalon reads.

BIT2 - Clears the recorded data of the first failure (address, expected data, and actual data).

BIT3 - Clears the recorded data of address overflow due to burst length (last address written to, failure status).

0x1C TG_BURST_LENGTH 7 1 Readable and Writeable Test Duration/Instruction Pattern Avalon burst length.
0x38 TG_RW_GEN_IDLE_COUNT 16 1 Readable and Writeable Test Duration/Instruction Pattern Number of cycles for which the traffic generator remains idle between a write block and the next read block.
0x3C TG_RW_GEN_LOOP_IDLE_COUNT 16 1 Readable and Writeable Test Duration/Instruction Pattern Number of cycles for which the traffic generator remains idle between a read block and the next write block.
0x40 TG_SEQ_START_ADDR_WR