External Memory Interfaces Stratix® 10 FPGA IP User Guide

ID 683741
Date 4/01/2024
Document Table of Contents

3.1.7. Stratix® 10 EMIF Architecture: PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in Stratix® 10 EMIF. Each PHY clock network spans only one bank.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

The PHY clock tree in Stratix® 10 devices can run as fast as 1.3 GHz. All Stratix® 10 external memory interfaces use the PHY clock trees.