Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

4.2.8. TX RSFEC

If you turn on Enable RS-FEC in the Low Latency 100G Ethernet Intel FPGA IP parameter editor, the IP core includes Reed-Solomon forward error correction (FEC) in both the receive and transmit datapaths.
The IP core implements Reed-Solomon FEC per Clause 91 of the IEEE Standard 802.3bj. The Reed-Solomon FEC algorithm includes the following modules:
  • 64B/66B to 256B/257B Transcoding
  • High-Speed RS-FEC(528,514) Reed-Solomon Encoder

When RS-FEC feature is enabled, the IP core instantiates an IOPLL to provide clock to the RS-FEC logic. In the IP core version 18.1 and after, you can dynamically control the RS-FEC block.