Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

4.2. Low Latency 100G Ethernet Intel FPGA IP Core TX Datapath

The TX MAC module receives the client payload data with the destination and source addresses and then adds, appends, or updates various header fields in accordance with the configuration specified. The MAC does not modify the destination address, the source address, or the payload received from the client. However, the TX MAC module adds a preamble (if the IP core is not configured to receive the preamble from user logic), pads the payload of frames greater than eight bytes to satisfy the minimum Ethernet frame payload of 46 bytes, and if you set Enable TX CRC insertion or turn on flow control, calculates the CRC over the entire MAC frame. (If padding is added, it is also included in the CRC calculation. If you turn off Enable TX CRC insertion , the client must provide the CRC bytes and must provide frames that have a minimum size of 64 bytes and therefore do not require padding). The TX MAC module always inserts IDLE bytes to maintain an average IPG.

The Low Latency 100G Ethernet Intel FPGA IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

Figure 6. Typical Client Frame at the Transmit InterfaceIllustrates the changes that the TX MAC makes to the client frame when Enable preamble passthrough is turned off. This figure uses the following notational conventions:
  • <p> = payload size, which is arbitrarily large.
  • <s> = number of padding bytes (0–46 bytes)
  • <g> = number of IPG bytes (full bytes)

The following sections describe the functions performed by the TX MAC:

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