Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

1.1. Low Latency 100G Ethernet Intel FPGA IP Core Supported Features

The IP core is designed to the IEEE 802.3ba-2010 and 802.3bj High Speed Ethernet Standard available on the IEEE website (www.ieee.org). The MAC provides cut-through frame processing to optimize latency, and supports full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets. All Low Latency 100G Ethernet Intel FPGA IP core variations include both a MAC and a PHY, and all variations are in full-duplex mode. These IP core variations offer the following features:

  • PHY features:
    • Soft PCS logic that interfaces seamlessly to Intel® Stratix® 10 FPGA 25.78125 Gbps serial transceivers.
    • CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
    • Auto negotiation (AN) as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6.
    • Link training (LT) as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G Ethernet Consortium Schedule Draft 1.6.
    • Optional Reed-Solomon forward error correction RS-FEC(528,514).
  • Frame structure control features:
    • Support for jumbo packets.
    • TX and RX CRC pass-through control.
    • Optional TX CRC generation and insertion.
    • RX and TX preamble pass-through options for applications that require proprietary user management information transfer.
    • TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the Low Latency 100G Ethernet Intel FPGA IP Ethernet connection.
    • Inter-packet Gap modulation capability for alignment marker insertion.
  • Frame monitoring and statistics:
    • RX CRC checking and error reporting.
    • Optional RX strict SFD checking per IEEE specification.
    • RX malformed packet checking per IEEE specification.
    • Received control frame type indication.
    • Optional statistics counters.
    • Optional fault signaling reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
  • Flow control:
    • Optional IEEE 802.3 Clause 31 Ethernet flow control operation using the pause registers or pause interface.
    • Optional priority-based flow control that complies with the IEEE Standard 802.1Qbb-2011—Amendment 17: Priority-based Flow Control, using the pause registers for fine control.
    • Pause frame filtering control.
  • Debug and testability features:
    • Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
    • TX error insertion capability supports test and debug.
    • Optional access to Native PHY Debug Master Endpoint (NPDME) for debugging or monitoring PHY signal integrity.
  • User system interfaces:
    • Avalon® Memory-Mapped (Avalon-MM) management interface to access the IP core control and status registers.
    • Avalon® -ST data path interface connects to client logic with the start of frame in the most significant byte (MSB). Interface has data width 512 bits, to ensure the data rate despite this RX client interface SOP alignment and RX and TX preamble pass-through option.
    • Hardware and software reset control.

For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet Standard.