Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

4.2.7. TX PCS

The soft TX PCS implements MII encoding, scrambling, block tagging, shifting, and interleaving. The 66-bit output stream is input to the hard PCS and PMA block.
Figure 7. High Level Block Diagram of the Soft TX PCS

The Hard PCS and PMA blocks are configured in 66:64 bit basic generic 25G PCS mode. These blocks use FIFOs in elastic-buffer mode. The PMA operates at 25.78125 Gbps.