Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

6.9. Flow Control Interface

Flow Control Interface signals become available when you turn on Enable MAC Flow Control in the parameter editor.
Table 21.  Flow Control Signals

Signal Name






This signal is available if you specify pause on PFC.

The signal indicates to the MAC whether XON or XOFF Pause or PFC flow control frame should be sent.
  • FCQN = 1 for Pause
  • FCQN = 1 ~ 8 for PFC
The request for XON/XOFF flow control frame transmission can be done in either 1 or 2-bit request mode.

1-bit mode request model:

The IP core ignores pause_insert_tx1[(FCQN-1):0].

The following encoding is defined:
  • 0: No request
  • 0 to 1: Generate XOFF request
  • 1: Continue to generate XOFF request
  • 1 to 0: Generate XON request

2-bit mode request model:

The higher-order bit is in pause_insert_tx1[(FCQN-1):0] and the lower-order bit is in pause_insert_tx0[(FCQN-1):0].

The XON/XOFF request is a level-based request.

The following encoding is defined:

  • 00: No further XON/XOFF request. In an XON/XOFF flow control frame is in progress, it is sent.
  • 01: Generate XON flow control frame and continuously sends them thereafter
  • 10: Generate XOFF flow control frame and continuously sends them thereafter
  • 11: Invalid request
pause_receive_rx[(FCQN-1):0] Output

Each pause_receive_rx[(FCQN-1):0] bit indicates the corresponding queue is being paused.

This is a level-based signal.