Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

2.5.1. Pin Assignments

When you integrate your Low Latency 100G Ethernet Intel FPGA IP core instance in your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals until you are ready to map the design to hardware.

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