Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.11. Auto Negotiation Status Register 2

This register provides the upper bits of the AN RX Base page received from the link partner.

Offset: 0xC8

Access: RO

Auto Negotiation Status Register 2 Fields

Bit Name Description Access Reset
31:0 lp_base_page_high Link Partner Base Page (upper bits)

[29:5]: Link partner Technology Ability bits

[4:0]: TX Nonce bits

RO 0x0

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