Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Public
Document Table of Contents

6.1. TX MAC Interface to User Logic

The Low Latency 100G Ethernet Intel FPGA IP core TX client interface employs the Avalon® streaming interface protocol. The Avalon® streaming interface protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:

  • Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
  • The SOP must always be in the MSB, simplifying the interpretation and processing of incoming data.
  • A valid signal qualifies signals from source to sink.
  • The sink applies backpressure to the source by using the ready signal. The source typically responds to the deassertion of the ready signal from the sink by driving the same data until the sink can accept it. The readyLatency defines the relationship between assertion and deassertion of the ready signal, and cycles which are considered to be ready for data transfer. The readyLatency on the TX client interface is zero cycle.

The client acts as a source and the TX MAC acts as a sink in the transmit direction.

Table 12.  Signals of the Avalon® TX Client Streaming InterfaceAll interface signals are clocked by the clk_txmac clock.

Signal Name

Direction

Description

clk_txmac Output

The TX clock for the IP core is clk_txmac. The frequency of this clock is 390.625  MHz.

l8_tx_data[511:0]

Input

TX data. If the preamble pass-through feature is enabled, data begins with the preamble.

The Low Latency 100G Ethernet Intel FPGA IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

You must send each TX data packet without intermediate IDLE cycles. Therefore, you must ensure your application can provide the data for a single packet in consecutive clock cycles. If data might not be available otherwise, you must buffer the data in your design and wait to assert l8_tx_startofpacket when you are assured the packet data to send on l8_tx_data[511:0] is available or will be available on time.

l8_tx_empty[5:0]

Input

Indicates the number of empty bytes on l8_tx_data[511:0] when l8_tx_endofpacket is asserted.

l8_tx_startofpacket

Input

When asserted, indicates the start of a packet. The packet starts on the MSB.

l8_tx_endofpacket

Input

When asserted, indicates the end of packet.

l8_tx_ready

Output

When asserted, the MAC is ready to receive data. The l8_tx_ready signal acts as an acknowledge. The source drives l8_tx_valid and l8_tx_data[511:0], then waits for the sink to assert l8_tx_ready. The readyLatency is zero cycle, so that the IP core accepts valid data in the same cycle in which it asserts l8_tx_ready.

The l8_tx_ready signal indicates the MAC is ready to receive data in normal operational mode. However, the l8_tx_ready signal might not be an adequate indication following reset. To avoid sending packets before the Ethernet link is able to transmit them reliably, you should ensure that the application does not send packets on the TX client interface until after the tx_lanes_stable signal is asserted.

l8_tx_valid

Input

When asserted l8_tx_data is valid. This signal must be continuously asserted between the assertions of l8_tx_startofpacket and l8_tx_endofpacket for the same packet.

l8_tx_error Input When asserted in an EOP cycle (while l8_tx_endofpacket is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.
l8_txstatus_valid Output When asserted, indicates that l8_txstatus_data and l8_txstatus_error[6:0] are driving valid data.
l8_txstatus_data[39:0] Output

Specifies information about the transmit frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
l8_txstatus_error[6:0] Output

Specifies the error type in the transmit frame. The following fields are defined:

  • Bits[6:3]: Reserved
  • Bit[2]: Payload length error
  • Bit[1]: Oversized frame
  • Bit[0]: Reserved.
This signal is valid when l8_txstatus_valid is asserted.
Figure 18. Traffic on the TX Avalon-ST Client Interface for Low Latency 100G Ethernet Intel FPGA IP Shows typical traffic for the TX client interface of the IP core.

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