Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

2.5.3. Placement Settings for the Low Latency 100G Ethernet Intel FPGA IP Core

The Intel® Quartus® Prime Pro Edition software provides the options to specify design partitions and Logic Lock regions for block-based design, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.

The appropriate floorplan is always design-specific, and depends on your full design.

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