Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
Public
Document Table of Contents

7.8.23. Link Training Config Register for Lane 1

Provides CSRs for the following link training features:
  • LT PRBS Pattern Select for lane 1
  • LT PRBS Seed for lane 1

Offset: 0xE0

Access: RW

Link Training Config Register for Lane 1 Fields

Bit Name Description Access Reset
26:16 lt_prbs_seed_ln1 Link Training PRBS Seed for Lane 1

Sets the initial seed for PRBS. Default value is 11'h645

RW 0x645
2:0 lt_prbs_pattern_select_ln1 Link Training PRBS Pattern Select for Lane 1

0: Use Clause 92 Polynomial 0

1: Use Clause 92 Polynomial 1

2: Use Clause 92 Polynomial 2

3: Use Clause 92 Polynomial 3

4: Use Clause 72 Polynomial (if CL72 PRBS parameter is enabled)

All other settings reserved

  • Default value for lane 1 is 1
RW 0x1

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