Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

ID 683100
Date 2/16/2022
Document Table of Contents

6.2. RX MAC Interface to User Logic

The Low Latency 100G Ethernet Intel FPGA IP core RX datapath employs the Avalon® streaming interface protocol. The Avalon® streaming interface protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:

  • Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
  • The SOP must always be in the MSB, simplifying the interpretation and processing of data you receive on this interface.
  • A valid signal qualifies signals from source to sink.

The RX MAC acts as a source and the client acts as a sink in the receive direction.

Table 13.  Signals of the Avalon® RX Client Streaming InterfaceAll interface signals are clocked by the clk_rxmac clock.




clk_rxmac Output

The RX clock for the IP core is clk_rxmac. The IP core recovers this clock from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625  MHz.



RX data. Bit 511 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard.



Indicates the number of empty bytes on l8_rx_data[511:0] when l8_rx_endofpacket is asserted, starting from the least significant byte (LSB).



When asserted, indicates the start of a packet. The packet starts on the MSB.



When asserted, indicates the end of packet.

In the case of an undersized packet, or in the case of a packet that is exactly 64 bytes long, l8_rx_startofpacket and l8_rx_endofpacket are asserted in the same clock cycle.

l8_rx_error[5:0] Output Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only.

The individual bits report different types of errors:

  • Bit [0]: Malformed packet error. If this bit has the value of 1, the packet is malformed. The IP core identifies a malformed packet when it receives a control character that is not a terminate character, while receiving the packet.
  • Bit [1]: CRC error. If this bit has the value of 1, the IP core detected a CRC error in the frame.
  • Bit [2]: undersized payload. If this bit has the value of 1, the frame size is between nine and 63 bytes, inclusive. The IP core does not recognize an incoming frame of size eight bytes or less as a frame, and those cases are not reported here. The l8_rx_error[1] bit also signals an FCS error.
  • Bit [3]: oversized payload. If this bit has the value of 1, the frame size is greater than the maximum frame size programmed in the RXMAC_SIZE_CONFIG register at offset 0x506.
  • Bit [4]: payload length error. If this bit has the value of 1, the payload received in the frame did not match the length field value, and the value in the length field is less than 1536 bytes.
  • Bit [5]: Reserved.


When asserted, indicates that RX data is valid. Only valid between the l8_rx_startofpacket and l8_rx_endofpacket signals.

This signal might be deasserted between the assertion of l8_rx_startofpacket and l8_rx_endofpacket.

l8_rxstatus_valid Output When asserted, indicates that l8_rxstatus_data is driving valid data. This signal behaves identically to the l8_rx_endofpacket signal.
l8_rxstatus_data[39:0] Output

Specifies information about the received frame. The following fields are defined:

  • Bit[39]: When asserted, indicates a PFC frame
  • Bit[38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
Figure 19. Traffic on the RX Avalon-ST Client Interface for Low Latency 100G Ethernet Intel FPGA IPShows typical traffic for the RX client interface of the IP core.

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