Low Latency 100G Ethernet Intel® FPGA IP Core User Guide: For Intel® Stratix® 10 Devices

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ID 683100
Date 2/16/2022
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4.3.5. Low Latency 100G Ethernet Intel FPGA IP Core Malformed Packet Handling

The malformed packet handling feature ensures the client receives the expected SOP-EOP sequences on the RX client interface. While receiving an incoming packet from the Ethernet link, the Low Latency 100G Ethernet Intel FPGA IP core expects to detect a terminate character at the end of the packet. When it detects an expected terminate character, the IP core generates an EOP on the client interface. However, sometimes the IP core detects an unexpected control character when it expects a terminate character. The Low Latency 100G Ethernet Intel FPGA IP core detects and handles the following forms of malformed packets:

  • If the IP core detects an Error character, it generates an EOP and asserts a malformed packet error (l8_rx_error[0]). If the IP core subsequently detects a terminate character, it does not generate another EOP indication.
  • If the IP core detects any other control character (for example, an IDLE or Start character) when it is waiting for an EOP indication (terminate character), the IP core generates an EOP indication, asserts a malformed packet error (l8_rx_error[0]), and asserts a CRC error (l8_rx_error[1]). If the IP core subsequently detects a terminate character, it does not generate another EOP indication.

When the IP core receives a packet that contains an error deliberately introduced on the Ethernet link using the Low Latency 100G Ethernet Intel FPGA TX error insertion feature, the IP core identifies it as a malformed packet.

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